Exploiting Symmetry When Verifying Transistor-level Circuits by Symbolic Trajectory Evaluation

نویسندگان

  • Manish Pandey
  • Randal E. Bryant
چکیده

In this paper we describe the use of symmetry for verii-cation of transistor-level circuits by symbolic trajectory evaluation. We show that exploiting symmetry can allow one to verify systems several orders of magnitude larger than otherwise possible. We classify symmetries in circuits as structural symmetries, arising from similarities in circuit structure, data symmetries, arising from similarities in the handling of data values, and mixed structural-data symmetries. We use graph isomorphism testing and symbolic simulation to verify the symmetries in the original circuit. Using conservative approximations, we partition a circuit to expose the symmetries in its components, and construct reduced system models which can be veriied eeciently. We have veriied Static Random Access Memory circuits with up to 1.5 Million transistors.

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تاریخ انتشار 1997